`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:  X-Speed.com.cn
// Engineer: yansf
// 
// 
// Create Date:    01/14/2024
// Design Name: 
// Module Name:    NH22
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module NH22_TOP(
			// ------------- with CPU
				I2C_SCL_CONFIG, 
				I2C_SDA_CONFIG, 
				I2C_SCL_SLAVE, 
				I2C_SDA_SLAVE, 
				nRST_REQ_FrCPU, 
				nRST_PORESET_toCPU,
				nRst_Button_Fr_Cpu,
			// ------------- WDT
				WDT_WDI,
				nWDT_MR, 
				nRST_FrWDT, 
			// ------------- Bypass
				BYPASS_DC_EN,
				BYPASS_PULSE_EN,
				FPGA_BYPASS_EN,
			// ------------- LED
				LED_ERROR_POSITIVE,
				LED_ERROR_NEGATIVE,
				LED_BYPASS,
			// ------------- CONSOLE  DET
				RS485_422_RE0_DET_FPGA,
				RS485_DE0_ISO_DET_FPGA,
				RS232_TX_EN0_DET_FPGA,
				RS422_DE0_DET_FPGA,
				RS485_422_RE1_DET_FPGA,
				RS485_DE1_ISO_DET_FPGA,
				RS232_TX_EN1_DET_FPGA,
				RS422_DE1_DET_FPGA,
			// ------------- CONSOLE  CONTROL
				RS485_RE0_B3_3V3,
				RS485_DE0_B3_3V3,
				RS485_RE1_B3_3V3,
				RS485_DE1_B3_3V3,
				RS422_DE1_B3,
				RS422_DE0_B3,
				RS232_TX_EN1_B3,
				RS232_TX_EN0_B3,
			// ------------- CONFIG
				BOARD_CFG0, 
				BOARD_CFG1, 
				BOARD_CFG2, 
				BOARD_CFG3, 
			//-------------- INT SIGNAL
				nPM_FIQ_OUT,				
			//-------------- BYPASS VOLTAGE DET
				BP_VOLTAGE_DIODE_DET,
				BP_VOL_OV,
				BP_VOL_UV,
			//-------------- ERROR OUT
				ERROR_BYPASS_EN,
			//-------------- CPU TO FPGA UART SIGNALS
				UART2_TX_B3,
				UART2_RX_B3,
				UART3_TX_B3,
				UART3_RX_B3,
			//-------------- FPGA TO CONSOLE_CHIP UART SIGNALS
				UART2_RX_CON_3V3,
				UART2_TX_CON_3V3,
				UART3_RX_CON_3V3,
				UART3_TX_CON_3V3,
			//-------------- 24Mhz CLK INPUT
				CLK_24M_IN
);

// ------------- with CPU
input 	I2C_SCL_SLAVE;
inout 	I2C_SCL_CONFIG;
inout 	I2C_SDA_CONFIG, I2C_SDA_SLAVE;
output 	nRST_PORESET_toCPU;
input 	nRST_REQ_FrCPU;
input	nRst_Button_Fr_Cpu;
// ------------- WDT
output 	WDT_WDI;
output 	nWDT_MR;
input 	nRST_FrWDT;
// ------------- Bypass
output 	BYPASS_DC_EN;
output	BYPASS_PULSE_EN;
output	FPGA_BYPASS_EN;
// ------------- LED
output 	LED_ERROR_POSITIVE;
output  LED_ERROR_NEGATIVE;
output	LED_BYPASS;
// ------------- Power & Reset
input 	nPM_FIQ_OUT;
// ------------- CONFIG
input 	BOARD_CFG0, BOARD_CFG1, BOARD_CFG2, BOARD_CFG3;
//-------------- CONSOLE DET
input	RS485_422_RE0_DET_FPGA;
input	RS485_DE0_ISO_DET_FPGA;
input	RS232_TX_EN0_DET_FPGA;
input	RS422_DE0_DET_FPGA;
input	RS485_422_RE1_DET_FPGA;
input	RS485_DE1_ISO_DET_FPGA;
input	RS232_TX_EN1_DET_FPGA;
input	RS422_DE1_DET_FPGA;
//-------------- CONSOLE CONTROL
output	RS485_RE0_B3_3V3;
output	RS485_DE0_B3_3V3;
output	RS485_RE1_B3_3V3;
output	RS485_DE1_B3_3V3;
output	RS422_DE1_B3;
output	RS422_DE0_B3;
output	RS232_TX_EN1_B3;
output	RS232_TX_EN0_B3;
//--------------- BYPASS DET
input  	BP_VOLTAGE_DIODE_DET;
input	BP_VOL_OV;
input	BP_VOL_UV;
//--------------- CLK
input	CLK_24M_IN;
//--------------- CPU TO FPGA UART SIGNAL
input	UART2_TX_B3;
output	UART2_RX_B3;
input	UART3_TX_B3;
output	UART3_RX_B3;
//--------------- FPGA TO CHIP UART SIGNAL
input	UART2_RX_CON_3V3;
output	UART2_TX_CON_3V3;
input	UART3_RX_CON_3V3;
output	UART3_TX_CON_3V3;

//--------------ERROR ERROR RELAY OUTPUT
output	ERROR_BYPASS_EN;


// -------------------------------- Inter Wires between uuts---------------------------------
wire 				CLK_24M_IN;
wire 				Clk_5ms;
wire				Clk_1s;
wire 				nSysRst;
wire 				nRST_FrWDT;
wire				nRST_REQ_FrCPU;
wire 				nRst_Button_Fr_Cpu;
wire 				nRST_PORESET_toCPU;
wire				r_Rst_Botton_Reseted;
wire				r_Req_Reseted;
wire				r_wdt_Reseted;
wire				rst_reason_clr;
wire				nPM_FIQ_OUT;
wire           		w_Bypass_Control;
wire				bp_vol_error;
wire  				com1_mode_error;
wire				com2_mode_error;
wire 				error_out_ctrl;
wire	[1:0]		Com1_Console_mode_ctrl;
wire	[1:0]		Com2_Console_mode_ctrl;
wire				UART2_TX_B3;
wire				UART2_RX_B3;
wire				UART3_TX_B3;
wire				UART3_RX_B3;
wire				UART2_RX_CON_3V3;
wire 				UART2_TX_CON_3V3;
wire				UART3_RX_CON_3V3;
wire 				UART3_TX_CON_3V3;
wire 				WDT_WDI;
wire 				w_WDT_En;	
wire 				w_WDT_Feed;
wire 	[7:0]		w_Watchdog_Time;
wire    [7:0] 		w_WDT_Time_Cnt;
wire 				BYPASS_STATUS_IN;
wire 	[2:0]		Com1_Console_mode_det;
wire 	[2:0]		Com2_Console_mode_det;
wire				RS485_422_RE0_DET_FPGA;
wire				RS485_DE0_ISO_DET_FPGA;
wire				RS232_TX_EN0_DET_FPGA;
wire				RS422_DE0_DET_FPGA;
wire				RS485_422_RE1_DET_FPGA;
wire				RS485_DE1_ISO_DET_FPGA;
wire				RS232_TX_EN1_DET_FPGA;
wire				RS422_DE1_DET_FPGA;
wire				BP_VOL_OV;
wire				BP_VOL_UV;
wire 				BP_VOLTAGE_DIODE_DET;
wire 				BOARD_CFG0, BOARD_CFG1, BOARD_CFG2, BOARD_CFG3;
wire				LED_BYPASS;
wire				BYPASS_DC_EN;
wire        		RS485_RE0_B3_3V3;
wire 				RS485_DE0_B3_3V3;
wire  				RS485_RE1_B3_3V3;
wire 				RS485_DE1_B3_3V3;
wire 				RS422_DE1_B3;
wire 				RS422_DE0_B3;
wire 				RS232_TX_EN1_B3;
wire 				RS232_TX_EN0_B3;
wire				nWDT_MR;
wire				BYPASS_PULSE_EN;
wire				w_total_error;


// ---------------------------------- Module Instantiation --------------------------------------

// -------------------------------------------
//assign CLK_25M_OUT = 1'bz;
//assign CLK_25M_IN = 1'bz;
// Use Internal Oscillator
// defparam OSCH_inst.NOM_FREQ = "2.08";// This is the default frequency
/*
defparam OSCH_inst.NOM_FREQ = "24.18";
OSCH 	OSCH_inst( 
	.STDBY( 1'b0 ), // 0=Enabled, 1=Disabled, also Disabled with Bandgap=OFF
	.OSC( CLK_24M_IN ),
	.SEDSTDBY(  )// this signal is not required if not using SED
);	
*/

// ------------------------------- CLK and Reset
ClkAndRst	inst_ClkAndRst(
	//-----------clk
	.Clk				( CLK_24M_IN ),
	.Clk_5ms			( Clk_5ms ),
	.Clk_1s				( Clk_1s ),
	//-----------reset source
	.nRst_FrWDT			( nRST_FrWDT ), 
	.nRST_REQ_FrCPU		( nRST_REQ_FrCPU ),  
	.nRst_Button_Fr_Cpu	( nRst_Button_Fr_Cpu ),
	// ------ out
	.nRst_Global		( nSysRst ),
	.nRST_PORESET_toCPU	( nRST_PORESET_toCPU ),
	//--------rst register
	.r_Rst_Botton_Reseted	( r_Rst_Botton_Reseted ),
	.r_Req_Reseted      ( r_Req_Reseted ),
	.r_wdt_Reseted		( r_wdt_Reseted ),
	//--------reset cause 
	.rst_reason_clr		( rst_reason_clr ),
	.nPM_FIQ_OUT		( nPM_FIQ_OUT )
);
			

// -------------uart console mode set
ConsoleCtrl inst_ConsoleCtrl(
	//-----------input clk
	.Clk				( CLK_24M_IN ), 
	//-----------input RESET signals
	.nRst				( nSysRst ),
	//-----------com1,com2 console mode setting register
	.Com1_Console_mode_ctrl		( Com1_Console_mode_ctrl ),
	.Com2_Console_mode_ctrl		( Com2_Console_mode_ctrl ),
	//-----------CPU to FPGA uart 3.3V signals
	.UART2_TX_B3		( UART2_TX_B3 ),
	.UART2_RX_B3		( UART2_RX_B3 ),
	.UART3_TX_B3		( UART3_TX_B3 ),
	.UART3_RX_B3		( UART3_RX_B3 ),
	//-----------FPGA to CHIP uart 3.3V signals
	.UART2_RX_CON_3V3	( UART2_RX_CON_3V3 ),
	.UART2_TX_CON_3V3	( UART2_TX_CON_3V3 ),
	.UART3_RX_CON_3V3	( UART3_RX_CON_3V3 ),
	.UART3_TX_CON_3V3	( UART3_TX_CON_3V3 ),
	//-----------RS232/RS485/RS422 mode ctrl
	.RS485_RE0_B3_3V3	( RS485_RE0_B3_3V3 ),
	.RS485_DE0_B3_3V3	( RS485_DE0_B3_3V3 ),
	.RS485_RE1_B3_3V3	( RS485_RE1_B3_3V3 ),
	.RS485_DE1_B3_3V3	( RS485_DE1_B3_3V3 ),
	.RS422_DE1_B3		( RS422_DE1_B3 ),
	.RS422_DE0_B3		( RS422_DE0_B3 ),
	.RS232_TX_EN1_B3	( RS232_TX_EN1_B3 ),
	.RS232_TX_EN0_B3	( RS232_TX_EN0_B3 )
);


// -------------WDT
FeedWDT	inst_FeedWDT(
	.Clk				( CLK_24M_IN ), 
	.nRst				( nSysRst ),
	.Clk_5ms			( Clk_5ms ),
	.Clk_1s				( Clk_1s ),
	// ---------outputs
	.WDI				( WDT_WDI ), 
	.WDT_EN				( w_WDT_En ), 
	.CPU_Feed			( w_WDT_Feed ), 
	.WDT_MR				( nWDT_MR ),
	.TimeOutSecs		( w_Watchdog_Time ),
	.Time_Cnt			( w_WDT_Time_Cnt )
);

// --------------------------------- LED
LEDCtrl	inst_LEDCtrl(
	.Clk				( CLK_24M_IN ), 
	.nRst				( nSysRst ),
	//-----------LED_OUT
	.LED_BYPASS			( LED_BYPASS ),
	.ERROR_terminal_led_p	( LED_ERROR_POSITIVE ),
	.ERROR_terminal_led_n	( LED_ERROR_NEGATIVE ),
	//-----------LED CONTROL INPUT SIGNAL
	.BYPASS_STATUS_IN		( BYPASS_STATUS_IN ),
	//-----------ERROR CAUSE INPUT SIGNALS
	.error_out_ctrl			( error_out_ctrl ),
	.nRST_REQ_FrCPU			( nRST_REQ_FrCPU ),
	.w_total_error			( w_total_error )
);


// -----------------Communicate with CPU----------------
CPU_Interface	inst_CPU_Interface(
	.Clk				( CLK_24M_IN ), 
	.nRst				( nSysRst ),
	.I2C_SCL_SLAVE		( I2C_SCL_SLAVE ), 
	.I2C_SDA_SLAVE		( I2C_SDA_SLAVE ),
	// ---------------- input --------------------------
	.Board_Ver			( {BOARD_CFG3, BOARD_CFG2, BOARD_CFG1, BOARD_CFG0} ), //CONFIG RESISTORS
	.b_WDT_OverTime		( r_wdt_Reseted ),  
	.nReq_Reset			( r_Req_Reseted ),
	.n_Rst_Botton_Reset	( r_Rst_Botton_Reseted ),
	.BYPASS_STATUS_IN 	( BYPASS_STATUS_IN ),
	// ---------------Output Regs -----------------------
	.r_Watchdog_Time	( w_Watchdog_Time ),    //WDT OVER TIME SETTING 0~255S
	.r_WDT_Feed			( w_WDT_Feed ), 
	.r_WDT_En			( w_WDT_En ), 
	.r_Bypass_Control	( w_Bypass_Control ),  //1'bx, software ctrl bypass bit
	//----------------debug
	.WDT_Time_Cnt		( w_WDT_Time_Cnt ),  //time counts from last time wdi change
	//-----COM1,COM2 console mode ctrl reg
	.r_Console_Com1_Mode_Ctrl			( Com1_Console_mode_ctrl ),
	.r_Console_Com2_Mode_Ctrl			( Com2_Console_mode_ctrl ),
	//-----error terminal
	.r_error_terminal_en				( error_out_ctrl ),
	//-----error signal
	.bp_vol_error						( bp_vol_error ),
	.com1_mode_error					( com1_mode_error ),
	.com2_mode_error					( com2_mode_error ),
	//-----reset cause clear bit
	.rst_reason_clr						( rst_reason_clr ),
	//-----
	.Com2_Console_mode_det				( Com2_Console_mode_det ),
	.Com1_Console_mode_det				( Com1_Console_mode_det )
);


// ------------------------------- CPLD Update
//I2C Configuration
//I2C Config Address:0x40
// the frequency of wb_clk_i should be larger than 3MHz 
i2c_config inst_i2c_config (
	.wb_clk_i( CLK_24M_IN ), 
	.i2c1_scl( I2C_SCL_CONFIG ), 
	.i2c1_sda( I2C_SDA_CONFIG ), 
	.i2c1_irqo( )
);


// ------------------------------- Bypass AND ERROR TERMINAL CTRL
BypassCtrl	inst_BypassCtrl(
	//-------clk signal
	.Clk				( CLK_24M_IN ), 
	.Clk_5ms			( Clk_5ms ), 
	//-------reset source
	.nRst 				( nSysRst ), 
	//-------BYPASS CONTROL
    .Bypass_Control		( w_Bypass_Control ),
	//-------RELAY CONTROL----------
	.BP_BYPASS_PULSE	( BYPASS_PULSE_EN ),
	.BP_DC_POWER_EN		( BYPASS_DC_EN ),
	.FPGA_BYPASS_EN     ( FPGA_BYPASS_EN ),
	//-------ERROR reason input
	.bp_vol_error		( bp_vol_error ),
	.com1_mode_error    ( com1_mode_error ),
	.com2_mode_error	( com2_mode_error ),
	//-----------ERROR OUTPUT CONCTRL BY SOFTWARE
	.error_out_ctrl		( error_out_ctrl ),
	//-----------ERROR OUTPUT SIGNAL TO ERROR TERMINAL
	.error_terminal_en  ( ERROR_BYPASS_EN ),
	.r_Rst_Botton_Reseted	( r_Rst_Botton_Reseted ),
	.r_wdt_Reseted			( r_wdt_Reseted ),
	.nRST_REQ_FrCPU			( nRST_REQ_FrCPU ),
	.w_total_error			( w_total_error )
);


StatusDet inst_StatusDet(
//-----------input clk
	.Clk					( CLK_24M_IN ), 
	.Clk_5ms				( Clk_5ms ),
//-----------input RESET signals
	.nRst				( nSysRst ),
//-----------com1,com2 console mode det register
	.Com1_Console_mode_det	( Com1_Console_mode_det ),
	.Com2_Console_mode_det	( Com2_Console_mode_det ),
//-----------CHIP to FPGA mode DET signals
	.RS485_422_RE0_DET_FPGA		( RS485_422_RE0_DET_FPGA ),
	.RS485_DE0_ISO_DET_FPGA		( RS485_DE0_ISO_DET_FPGA ),
	.RS232_TX_EN0_DET_FPGA		( RS232_TX_EN0_DET_FPGA ),
	.RS422_DE0_DET_FPGA			( RS422_DE0_DET_FPGA ),
	.RS485_422_RE1_DET_FPGA		( RS485_422_RE1_DET_FPGA ),
	.RS485_DE1_ISO_DET_FPGA		( RS485_DE1_ISO_DET_FPGA ),
	.RS232_TX_EN1_DET_FPGA		( RS232_TX_EN1_DET_FPGA ),
	.RS422_DE1_DET_FPGA			( RS422_DE1_DET_FPGA ),
//-----------BYPASS voltage det to FPGA
	.BP_VOL_OV					( BP_VOL_OV ), //over voltage
	.BP_VOL_UV					( BP_VOL_UV ), //under voltage
	.BP_VOLTAGE_DIODE_DET		( BP_VOLTAGE_DIODE_DET ),
//-----------BYPASS control register input
	.BYPASS_EN					( w_Bypass_Control ),
//-----------BYPASS status det
	.BYPASS_STATUS				( BYPASS_STATUS_IN ),
//-----------Console mode setting
	.Com1_Console_mode_ctrl		( Com1_Console_mode_ctrl ),
	.Com2_Console_mode_ctrl		( Com2_Console_mode_ctrl ),
//-----------ERROR signal output
	.bp_vol_error				( bp_vol_error ),
	.Com1_mode_error			( com1_mode_error ),
	.Com2_mode_error			( com2_mode_error )
);

endmodule


/*
// synthesis translate_off

//---------------------------------------------------------------------------------------------
// ------------------------- Code for Simulation ----------------------------------------
//---------------------------------------------------------------------------------------------
*/


